import chisel3._
import chisel3.util._
import _root_.circt.stage.ChiselStage

class ALU extends Module {
    val io = IO(new Bundle {
        val a = Input(UInt(16.W))
        val b = Input(UInt(16.W))
        val fn = Input(UInt(2.W))
        val y = Output(UInt(16.W))
    })
    
    // ALU的默认输出值
    io.y := 0.U
    
    // 选择ALU的功能
    switch(io.fn) {
        is(0.U) {io.y := io.a + io.b}
        is(1.U) {io.y := io.a - io.b}
        is(2.U) {io.y := io.a | io.b}
        is(3.U) {io.y := io.a & io.b}
    }
}

//object ALU extends App {
//  println(getVerilogString(new ALU()))
//}
object ALU extends App {
  ChiselStage.emitSystemVerilogFile(
  new ALU(),
  firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
  )
}
